Making Memory Systems Efficient
Date and Time
Friday, December 9th, 2016 at 14:15.
Polacksbacken, ITC, room 1211.
Today’s memory systems use a large portion of the total processor energy due to inefficient data movement. The root cause of this is that we are using the same bandwidth-optimized designs we’ve had for the past 20-years: brute-force searches and global installations. If we dare to re-think memory systems from an efficiency-first perspective, we can dramatically improve efficiency (60% lower energy, 65% lower traffic, 30% lower latency) by applying smarter placement policies and providing efficient data access mechanisms. The key to all of this is perversely simple: flattening the memory hierarchy.
In this talk we will cover the Green Cache memory system technologies which combine the highly efficient “direct-to-data” memory access mechanisms with intelligent policies. This approach learns how to place and replicate data across the memory hierarchy (private, shared, and DRAM caches) to improve performance and reduce latency, while retaining compatibility with existing core and/or memory system designs.